Models
Our frontier reasoning model for science and engineering.
Set a thinking budget per request, from a quick reply to minutes of deliberate work.
Questions on process, devices, equipment and yield, graded by engineers who have done the work.
Runs long investigations on its own, and asks before it changes a real system.
Writes Python, Verilog, SystemVerilog and Tcl, trained against simulators, not just text.
A 256K context and your knowledge base: datasheets, process logs, ten years of notebooks.
Moves between them the way engineering teams actually work.
Case 01 · Root-cause analysis
Micius queries the MES, reads the wafer maps and compares equipment logs, then ranks the likely causes by confidence. It asks before changing anything on a real system.
Case 02 · Hardware verification
Micius turns a FIFO spec into SystemVerilog assertions and a testbench, runs the simulator, and points out the one corner case the random tests missed.
Case 03 · Ten years of notebooks
Working from the lab’s own records, Micius maps what was tried, what worked and which promising leads nobody followed up, and cites every claim.
Benchmark performance
Score, %. Higher is better. SemiBench: 2,400 questions written and graded by fab engineers.
| Benchmark | Micius-V1.0-Flash | Model A | Model B |
|---|---|---|---|
| SemiBench | 78.6 | 61.2 | 57.8 |
| GPQA Diamond | 84.1 | 83 | 79.4 |
| AIME 2025 | 91.3 | 88.7 | 85.1 |
| SWE-bench Verified | 68.4 | 70.2 | 63.5 |
| VerilogEval v2 | 81.7 | 69.3 | 64 |
Try it in the app, build with the API, or run it in your own environment.
